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B2.24 CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1

The CPUACTLR2_EL1 provides IMPLEMENTATION DEFINED configuration and control options for the core.

Bit field descriptions

CPUACTLR2_EL1 is a 64-bit register, and is part of the IMPLEMENTATION DEFINED registers functional

group.

Reserved

Figure B2-20 CPUACTLR2_EL1 bit assignments

Reserved, [63:0]

Reserved for Arm internal use.

Configurations

CPUACTLR2_EL1 is common to the Secure and Non-secure states.

Usage constraints

Accessing the CPUACTLR2_EL1

The CPUACTLR2_EL1 can be written only when the system is idle. Arm recommends that you

write to this register after a powerup reset, before the MMU is enabled.

Setting many of these bits can cause significantly lower performance on your code. Therefore,

Arm strongly recommends that you do not modify this register unless directed by Arm.

This register can be read using MRS with the following syntax:

MRS <Xt>,<systemreg>

This register can be written using MSR with the following syntax:

MSR <systemreg>, <Xt>

This syntax is encoded with the following settings in the instruction encoding:

<systemreg> Op0 CRn Op1 CRm Op2

S3_0_C15_C1_1 3 c15 0 c1 1

Accessibility

This register is accessible in software as follows:

<syntax> Control Accessibility

E2H TGE NS EL0 EL1 EL2 EL3

S3_0_C15_C1_1 x x 0 - RW n/a RW

S3_0_C15_C1_1 x 0 1 - RW RW RW

S3_0_C15_C1_1 x 1 1 - n/a RW RW

'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.

B2 AArch64 system registers

B2.24 CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1

reserved.

B2-168

Non-Confidential

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