ARM Cortex-A76 Core User Manual

A9.2 Bypassing the CPU interface
The GIC CPU Interface is always implemented within the Cortex-A76 core.
However, you can disable it if you assert the GICCDISABLE signal HIGH at reset. If you disable the
GIC CPU interface, the input pins nVIRQ and nVFIQ can be driven by an external GIC in the SoC. GIC
system register access generates UNDEFINED instruction exceptions when the GICCDISABLE signal is
HIGH.
If the GIC is enabled, the input pins nVIRQ and nVFIQ must be tied off to HIGH. This is because the
internal GIC CPU interface generates the virtual interrupt signals to the cores. The nIRQ and nFIQ
signals are controlled by software, therefore there is no requirement to tie them HIGH.
A9 Generic Interrupt Controller CPU interface
A9.2 Bypassing the CPU interface
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A9-113
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core