ARM Cortex-A76 Core

B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1
AFSR1_EL1 provides additional IMPLEMENTATION DEFINED fault status information for exceptions that are
taken to EL1. This register is not used in Cortex-A76.
Bit field descriptions
AFSR1_EL1 is a 32-bit register, and is part of:
• The Exception and fault handling registers functional group.
• The IMPLEMENTATION DEFINED functional group.
031
RES0
Figure B2-7 AFSR1_EL1 bit assignments
RES0, [31:0]
Reserved, RES0.
Configurations
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1
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