ARM Cortex-A76 Core User Manual

B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1
The ID_ISAR0_EL1 provides information about the instruction sets implemented by the core in
AArch32.
Bit field descriptions
ID_ISAR0_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Divide Debug Coproc CmpBranch Bitfield BitCount Swap
RES0
Figure B2-49 ID_ISAR0_EL1 bit assignments
RES0, [31:28]
RES0 Reserved.
Divide, [27:24]
Indicates the implemented Divide instructions:
0x2 • SDIV and UDIV in the T32 instruction set.
• SDIV and UDIV in the A32 instruction set.
Debug, [23:20]
Indicates the implemented Debug instructions:
0x1 BKPT.
Coproc, [19:16]
Indicates the implemented Coprocessor instructions:
0x0 None implemented, except for instructions separately attributed by the architecture to
provide access to AArch32 System registers and System instructions.
CmpBranch, [15:12]
Indicates the implemented combined Compare and Branch instructions in the T32 instruction
set:
0x1 CBNZ and CBZ.
Bitfield, [11:8]
Indicates the implemented bit field instructions:
0x1 BFC, BFI, SBFX, and UBFX.
BitCount, [7:4]
Indicates the implemented Bit Counting instructions:
0x1 CLZ.
B2 AArch64 system registers
B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1
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B2-233
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core