ARM Cortex-A76 Core User Manual

B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
The ID_AA64PFR0_EL1 provides additional information about implemented core features in AArch64.
The optional Advanced SIMD and floating-point support is not included in the base product of the core.
Arm requires licensees to have contractual rights to obtain the Advanced SIMD and floating-point
support.
Bit field descriptions
ID_AA64PFR0_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 04 38 712 1116 15
EL3
handling
EL2
handling
EL1
handling
EL0
handling
AdvSIMD FP
20 1924 23
GIC
28 273263
RAS
RES0
60 59 56 55
CSV3 CSV2
Figure B2-45 ID_AA64PFR0_EL1 bit assignments
CSV3, [63:60]
0x0 This device does not disclose whether data loaded under speculation with a permission
or domain fault, if used as an address in a speculative load, can cause cache allocation.
0x1 Data loaded under speculation with a permission or domain fault cannot be used to
form an address or generate condition codes to be used by instructions newer than the
load in the speculative sequence. This is the reset value.
All other values reserved.
CSV2, [59:56]
0x0 This device does not disclose whether branch targets trained in one context can affect
speculative execution in a different context.
0x1 Branch targets trained in one context cannot affect speculative execution in a different
hardware described context. This is the reset value.
All other values reserved.
RES0, [55:32]
RES0 Reserved.
RAS, [31:28]
RAS extension version. The possible values are:
0x0 RAS extension is not present. This is the value if the core implementation does not
have ECC present.
0x1 Version 1 of the RAS extension is present. This is the value if the core implementation
has ECC present.
GIC, [27:24]
GIC CPU interface:
0x0 GIC CPU interface is disabled, GICCDISABLE is HIGH, or not implemented.
0x1 GIC CPU interface is implemented and enabled, GICCDISABLE is LOW.
B2 AArch64 system registers
B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
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B2-227
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core