AdvSIMD, [23:20]
Advanced SIMD. The possible values are:
0x1 Advanced SIMD, including Half-precision support, is implemented.
FP, [19:16]
Floating-point. The possible values are:
0x1 Floating-point, including Half-precision support, is implemented.
EL3 handling, [15:12]
EL3 exception handling:
0x1 Instructions can be executed at EL3 in AArch64 state only.
EL2 handling, [11:8]
EL2 exception handling:
0x1 Instructions can be executed at EL3 in AArch64 state only.
EL1 handling, [7:4]
EL1 exception handling. The possible values are:
0x1 Instructions can be executed at EL3 in AArch64 state only.
EL0 handling, [3:0]
EL0 exception handling. The possible values are:
0x2 Instructions can be executed at EL0 in AArch64 or AArch32 state.
Configurations
ID_AA64PFR0_EL1 is architecturally mapped to External register EDPFR.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-228
Non-Confidential
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