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ARM Cortex-A76 Core User Manual

ARM Cortex-A76 Core
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C4.2 ETM trace unit generation options and resources
The following table shows the trace generation options implemented in the Cortex-A76 ETM trace unit.
Table C4-1 ETM trace unit generation options implemented
Description Configuration
Instruction address size in bytes 8
Data address size in bytes 0
Data value size in bytes 0
Virtual Machine ID size in bytes 4
Context ID size in bytes 4
Support for conditional instruction tracing Not implemented
Support for tracing of data Not implemented
Support for tracing of load and store instructions as P0 elements Not implemented
Support for cycle counting in the instruction trace Implemented
Support for branch broadcast tracing Implemented
Number of events supported in the trace 4
Return stack support Implemented
Tracing of SError exception support Implemented
Instruction trace cycle counting minimum threshold
1
Size of Trace ID 7 bits
Synchronization period support Read-write
Global timestamp size 64 bits
Number of cores available for tracing 1
ATB trigger support Implemented
Low power behavior override
Not implemented
Stall control support Implemented
Support for overflow avoidance Not implemented
Support for using CONTEXTIDR_EL2 in VMID comparator Implemented
The following table shows the resources implemented in the Cortex-A76 ETM trace unit.
Table C4-2 ETM trace unit resources implemented
Description Configuration
Number of resource selection pairs implemented 8
Number of external input selectors implemented 4
Number of external inputs implemented
165, 4 CTI + 161 PMU
Number of counters implemented 2
C4 Embedded Trace Macrocell
C4.2 ETM trace unit generation options and resources
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
C4-393
Non-Confidential

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ARM Cortex-A76 Core Specifications

General IconGeneral
ArchitectureARMv8.2-A
MicroarchitectureCortex-A76
Pipeline Depth13 stages
FrequencyUp to 3.0 GHz
Process Technology7nm
Core TypeOut-of-order
NEONYes
Power EfficiencyImproved over Cortex-A75
Performance Improvement35% over Cortex-A75
Core Count1-4 cores per cluster
ISA SupportAArch64 and AArch32
Branch PredictionYes
L1 Data Cache32KB, per core
L2 Cache256KB or 512KB, per core
L3 CacheUp to 4MB
Memory SupportLPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)DynamIQ Shared Unit (DSU)
Cryptography ExtensionsYes
Virtualization SupportYes
L1 Cache64 KB per core

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