B2.98 TTBR0_EL3, Translation Table Base Register 0, EL3
The TTBR0_EL3 holds the base address of the translation table for the stage 1 translation of memory
accesses from EL3.
Bit field descriptions
TTBR0_EL3 is a 64-bit register.
BADDR[47:x]
4748 063
1
CnP
RES0
Figure B2-82 TTBR0_EL3 bit assignments
[63:48]
Reserved, RES0.
BADDR[47:x], [47:1]
Translation table base address, bits[47:x]. Bits [x-1:1] are RES0.
x is based on the value of TCR_EL1.T0SZ, the stage of translation, and the memory translation
granule size.
For instructions on how to calculate it, see the Arm
®
Architecture Reference Manual Armv8, for
Armv8-A architecture profile.
The value of x determines the required alignment of the translation table, that must be aligned to
2
x
bytes.
If bits [x-1:1] are not all zero, this is a misaligned translation table base address. Its effects are
CONSTRAINED UNPREDICTABLE, where bits [x-1:1] are treated as if all the bits are zero. The value
read back from those bits is the value written.
CnP, [0]
Common not Private. The possible values are:
0 CnP is not supported.
1 CnP is supported.
Configurations
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.98 TTBR0_EL3, Translation Table Base Register 0, EL3
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-283
Non-Confidential
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