ARM Cortex-A76 Core User Manual

B4.1 CPU interface registers
Each CPU interface block provides the interface for the Cortex-A76 core that interfaces with a GIC
distributor within the system.
The Cortex-A76 core only supports system register access to the GIC CPU interface registers. The
following table lists the three types of GIC CPU interface system registers supported in the Cortex-A76
core.
Table B4-1 GIC CPU interface system register types supported in the Cortex-A76 core.
Register prefix Register type
ICC Physical GIC CPU interface system registers.
ICV Virtual GIC CPU interface system registers.
ICH Virtual interface control system registers.
Access to virtual GIC CPU interface system registers is only possible at Non-secure EL1.
Access to ICC registers or the equivalent ICV registers is determined by HCR_EL2. See
B2.51 HCR_EL2, Hypervisor Configuration Register, EL2 on page B2-212.
For more information on the CPU interface, see the Arm
®
Generic Interrupt Controller Architecture
Specification.
B4 GIC registers
B4.1 CPU interface registers
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core