ARM Cortex-A76 Core User Manual

A4.3 Power domains
The Cortex-A76 core contains a core power domain (PDCPU), and a core top-level SYS power domain
(PDSYS) where all the Cortex-A76 core I/O signals go through.
The PDCPU power domain contains all enyo_cpu logic and part of the core asynchronous bridge that
belongs to the VCPU domain. The Advanced SIMD and floating-point unit are included in the PDCPU
power domain and is not supported as a separate power domain. The L1 and L2 RAMs are included in
the PDCPU power domain and are not part of a separate power domain.
The PDSYS power domain contains the part of the core asynchronous bridge that belongs to the DSU
power domain.
Note
There are additional system power domains in the DSU. See the Arm
®
DynamIQ
™
Shared Unit Technical
Reference Manual for information.
The following table shows the power domain that the Cortex-A76 core supports.
Table A4-1 Power domain description
Power
domain
Hierarchy Description
PDCPU<n>
u_vcpu
The domain includes the Advanced SIMD and floating-point block, the L1 and L2 TLBs, L1 and
L2 cache RAMs, and Debug registers that are associated with the Cortex-A76 core.
<n> is the number of Cortex-A76 cores. The number represents core 0, core 1, core 2, and core 3.
If a core is not present, the corresponding power domain is not present.
PDSYS Top-level
hierarchy and
everything
outside u_vcpu
The domain is the interface between Cortex-A76 and the DSU. It contains the cluster clock domain
logic of the CPU bridge. The CPU Bridge contains all asynchronous bridges for crossing clock
domains, and is split with one half of each bridge in the core clock domain and the other half in the
relevant cluster domain. All core I/O signals go through the CPU bridge and the SYS power
domain.
The domain is shared between the and hierarchies, and contains:
• Anything outside of the core power domain (u_vcpu hierarchy).
• u_cb_sys.
Clamping cells between power domains are inferred through power intent files rather than instantiated in
the RTL.
The following figure shows an example of the organization of the power domains.
A4 Power management
A4.3 Power domains
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A4-48
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core