ARM Cortex-A76 Core User Manual

Asynchronous bridge
SYS domain
VCPU voltage domain
Asynchronous bridge
CPU domain
L1
L2
VSYS voltage domain
PDCPU
PDSYS
Core
Figure A4-2 Cortex-A76 core power domain diagram at enyo_core level
The following figure shows the power domains in the DSU, where everything in the same color is part of
the same power domain. The example shows four Cortex-A76 cores. The number of Cortex-A76 cores
can vary, and the number of domains increases based on the number of Cortex-A76 cores present.
This example only shows the power domains that are associated with the Cortex-A76 cores, other power
domains are required for a DSU.
Cluster
Core 3
L2
PDCPU[3] domain
L1
Core 2
L2
PDCPU[2] domain
L1
Core 1
L2
PDCPU[1] domain
L1
Core 0
L2
PDCPU[0] domain
L1
Adv-SIMD/FP Adv-SIMD/FP Adv-SIMD/FP Adv-SIMD/FP
PDSYS
Figure A4-3 Cortex-A76 power domains at enyo_core level
A4 Power management
A4.3 Power domains
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reserved.
A4-49
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core