ARM Cortex-A76 Core User Manual

D9.1 ETM register summary
This section summarizes the ETM trace unit registers.
All ETM trace unit registers are 32-bit wide. The description of each register includes its offset from a
base address. The base address is defined by the system integrator when placing the ETM trace unit in
the Debug-APB memory map.
The following table lists all of the ETM trace unit registers.
Table D9-1 ETM trace unit register summary
Offset Name Type Reset Description
0x004
TRCPRGCTLR RW
0x00000000
D9.60 TRCPRGCTLR, Programming Control Register on page D9-570
0x00C
TRCSTATR RO
0x00000003
D9.68 TRCSTATR, Status Register on page D9-579
0x010
TRCCONFIGR RW UNK D9.20 TRCCONFIGR, Trace Configuration Register on page D9-521
0x018
TRCAUXCTLR RW
0x00000000
D9.5 TRCAUXCTLR, Auxiliary Control Register on page D9-503
0x020
TRCEVENTCTL0R RW UNK D9.26 TRCEVENTCTL0R, Event Control 0 Register on page D9-530
0x024
TRCEVENTCTL1R RW UNK D9.27 TRCEVENTCTL1R, Event Control 1 Register on page D9-532
0x02C
TRCSTALLCTLR RW UNK D9.67 TRCSTALLCTLR, Stall Control Register on page D9-578
0x030
TRCTSCTLR RW UNK D9.71 TRCTSCTLR, Global Timestamp Control Register
on page D9-582
0x034
TRCSYNCPR RW UNK D9.69 TRCSYNCPR, Synchronization Period Register on page D9-580
0x038
TRCCCCTLR RW UNK D9.7 TRCCCCTLR, Cycle Count Control Register on page D9-506
0x03C
TRCBBCTLR RW UNK D9.6 TRCBBCTLR, Branch Broadcast Control Register on page D9-505
0x040
TRCTRACEIDR RW UNK D9.70 TRCTRACEIDR, Trace ID Register on page D9-581
0x080
TRCVICTLR RW UNK D9.72 TRCVICTLR, ViewInst Main Control Register on page D9-583
0x084
TRCVIIECTLR RW UNK D9.73 TRCVIIECTLR, ViewInst Include-Exclude Control Register
on page D9-585
0x088
TRCVISSCTLR RW UNK D9.74 TRCVISSCTLR, ViewInst Start-Stop Control Register
on page D9-586
0x100
TRCSEQEVR0 RW UNK D9.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
on page D9-572
0x104
TRCSEQEVR1 RW UNK D9.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
on page D9-572
0x108
TRCSEQEVR2 RW UNK D9.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
on page D9-572
0x118
TRCSEQRSTEVR RW UNK D9.63 TRCSEQRSTEVR, Sequencer Reset Control Register
on page D9-574
0x11C
TRCSEQSTR RW UNK D9.64 TRCSEQSTR, Sequencer State Register on page D9-575
0x120
TRCEXTINSELR RW UNK D9.28 TRCEXTINSELR, External Input Select Register on page D9-533
0x140
TRCCNTRLDVR0 RW UNK D9.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1
on page D9-519
D9 ETM registers
D9.1 ETM register summary
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D9-495
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core