ARM Cortex-A76 Core User Manual

Table D9-1 ETM trace unit register summary (continued)
Offset Name Type Reset Description
0x144
TRCCNTRLDVR1 RW UNK D9.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1
on page D9-519
0x150
TRCCNTCTLR0 RW UNK D9.16 TRCCNTCTLR0, Counter Control Register 0 on page D9-515
0x154
TRCCNTCTLR1 RW UNK D9.17 TRCCNTCTLR1, Counter Control Register 1 on page D9-517
0x160
TRCCNTVR0 RW UNK D9.19 TRCCNTVRn, Counter Value Registers 0-1 on page D9-520
0x164
TRCCNTVR1 RW UNK D9.19 TRCCNTVRn, Counter Value Registers 0-1 on page D9-520
0x180
TRCIDR8 RO
0x00000000
D9.35 TRCIDR8, ID Register 8 on page D9-545
0x184
TRCIDR9 RO
0x00000000
D9.36 TRCIDR9, ID Register 9 on page D9-546
0x188
TRCIDR10 RO
0x00000000
D9.37 TRCIDR10, ID Register 10 on page D9-547
0x18C
TRCIDR11 RO
0x00000000
D9.38 TRCIDR11, ID Register 11 on page D9-548
0x190
TRCIDR12 RO
0x00000000
D9.39 TRCIDR12, ID Register 12 on page D9-549
0x194
TRCIDR13 RO
0x00000000
D9.40 TRCIDR13, ID Register 13 on page D9-550
0x1C0
TRCIMSPEC0 RW
0x00000000
D9.41 TRCIMSPEC0, Implementation Specific Register 0
on page D9-551
0x1E0
TRCIDR0 RO
0x28000EA1
D9.29 TRCIDR0, ID Register 0 on page D9-534
0x1E4
TRCIDR1 RO
0x4100F423
D9.30 TRCIDR1, ID Register 1 on page D9-536
0x1E8
TRCIDR2 RO
0x20001088
D9.31 TRCIDR2, ID Register 2 on page D9-537
0x1EC
TRCIDR3 RO
0x017B0100
D9.32 TRCIDR3, ID Register 3 on page D9-539
0x1F0
TRCIDR4 RO
0x11170004
D9.33 TRCIDR4, ID Register 4 on page D9-541
0x1F4
TRCIDR5 RO
0x2847089D
D9.34 TRCIDR5, ID Register 5 on page D9-543
0x200
TRCRSCTLRn RW UNK D9.61 TRCRSCTLRn, Resource Selection Control Registers 2-16
on page D9-571, n is 2, 15
0x280
TRCSSCCR0 RW UNK D9.65 TRCSSCCR0, Single-Shot Comparator Control Register 0
on page D9-576
0x2A0
TRCSSCSR0 RW UNK D9.66 TRCSSCSR0, Single-Shot Comparator Status Register 0
on page D9-577
0x300
TRCOSLAR WO
0x00000001
D9.50 TRCOSLAR, OS Lock Access Register on page D9-560
0x304
TRCOSLSR RO
0x0000000A
D9.51 TRCOSLSR, OS Lock Status Register on page D9-561
0x310
TRCPDCR RW
0x00000000
D9.52 TRCPDCR, Power Down Control Register on page D9-562
0x314
TRCPDSR RO
0x00000023
D9.53 TRCPDSR, Power Down Status Register on page D9-563
0x400
TRCACVRn RW UNK D9.3 TRCACVRn, Address Comparator Value Registers 0-7
on page D9-501
D9 ETM registers
D9.1 ETM register summary
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D9-496
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core