ARM Cortex-A76 Core User Manual

Table D9-1 ETM trace unit register summary (continued)
Offset Name Type Reset Description
0x480
TRCACATRn RW UNK D9.2 TRCACATRn, Address Comparator Access Type Registers 0-7
on page D9-499
0x600
TRCCIDCVR0 RW UNK D9.9 TRCCIDCVR0, Context ID Comparator Value Register 0
on page D9-508
0x640
TRCVMIDCVR0 RW UNK D9.75 TRCVMIDCVR0, VMID Comparator Value Register 0
on page D9-587
0x680
TRCCIDCCTLR0 RW UNK D9.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0
on page D9-507
0x688
TRCVMIDCCTRL0 RW UNK D9.76 TRCVMIDCCTLR0, Virtual context identifier Comparator
Control Register 0 on page D9-588
0xEE4
TRCITATBIDR RW UNK D9.42 TRCITATBIDR, Integration ATB Identification Register
on page D9-552
0xEEC
TRCITIDATAR WO UNK D9.46 TRCITIDATAR, Integration Instruction ATB Data Register
on page D9-556
0xEF4
TRCITIATBINR RO UNK D9.44 TRCITIATBINR, Integration Instruction ATB In Register
on page D9-554
0xEFC
TRCITIATBOUTR WO UNK D9.45 TRCITIATBOUTR, Integration Instruction ATB Out Register
on page D9-555
0xF00
TRCITCTRL RW
0x00000000
D9.43 TRCITCTRL, Integration Mode Control Register on page D9-553
0xFA0
TRCCLAIMSET RW UNK D9.15 TRCCLAIMSET, Claim Tag Set Register on page D9-514
0xFA4
TRCCLAIMCLR RW
0x00000000
D9.14 TRCCLAIMCLR, Claim Tag Clear Register on page D9-513
0xFA8
TRCDEVAFF0 RO UNK D9.21 TRCDEVAFF0, Device Affinity Register 0 on page D9-524
0xFAC
TRCDEVAFF1 RO UNK D9.22 TRCDEVAFF1, Device Affinity Register 1 on page D9-526
0xFB0
TRCLAR WO UNK D9.47 TRCLAR, Software Lock Access Register on page D9-557
0xFB4
TRCLSR RO
0x00000000
D9.48 TRCLSR, Software Lock Status Register on page D9-558
0xFB8
TRCAUTHSTATUS RO UNK D9.4 TRCAUTHSTATUS, Authentication Status Register
on page D9-502
0xFBC
TRCDEVARCH RO
0x47724A13
D9.23 TRCDEVARCH, Device Architecture Register on page D9-527
0xFC8
TRCDEVID RO
0x00000000
D9.24 TRCDEVID, Device ID Register on page D9-528
0xFCC
TRCDEVTYPE RO
0x00000013
D9.25 TRCDEVTYPE, Device Type Register on page D9-529
0xFE0
TRCPIDR0 RO
0x0000000B
D9.54 TRCPIDR0, ETM Peripheral Identification Register 0
on page D9-564
0xFE4
TRCPIDR1 RO
0x000000BD
D9.55 TRCPIDR1, ETM Peripheral Identification Register 1
on page D9-565
0xFE8
TRCPIDR2 RO
0x0000000B
D9.56 TRCPIDR2, ETM Peripheral Identification Register 2
on page D9-566
0xFEC
TRCPIDR3 RO
0x00000000
D9.57 TRCPIDR3, ETM Peripheral Identification Register 3
on page D9-567
D9 ETM registers
D9.1 ETM register summary
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-497
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core