ARM Cortex-A76 Core User Manual

Table D9-1 ETM trace unit register summary (continued)
Offset Name Type Reset Description
0xFD0
TRCPIDR4 RO
0x00000004
D9.58 TRCPIDR4, ETM Peripheral Identification Register 4
on page D9-568
0xFD4-0xFDC TRCPIDRn RO
0x00000000
D9.59 TRCPIDRn, ETM Peripheral Identification Registers 5-7
on page D9-569
0xFF0
TRCCIDR0 RO
0x0000000D
D9.10 TRCCIDR0, ETM Component Identification Register 0
on page D9-509
0xFF4
TRCCIDR1 RO
0x00000090
D9.11 TRCCIDR1, ETM Component Identification Register 1
on page D9-510
0xFF8
TRCCIDR2 RO
0x00000005
D9.12 TRCCIDR2, ETM Component Identification Register 2
on page D9-511
0xFFC
TRCCIDR3 RO
0x000000B1
D9.13 TRCCIDR3, ETM Component Identification Register 3
on page D9-512
D9 ETM registers
D9.1 ETM register summary
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D9-498
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core