ARM Cortex-A76 Core User Manual

A4.9 Power up and down sequences
The following approach allows taking the Cortex-A76 cores in the cluster in and out of coherence.
Core powerdown
To take a core out of coherence ready for core powerdown, the following power down steps must be
performed:
1. Save all architectural states.
2. Configure the GIC distributor to disable or reroute interrupts away from this core.
3. Set the CPUPWRCTLR.CORE_PWRDN_EN bit to 1 to indicate to the power controller that a
powerdown is requested.
4. Execute an ISB instruction.
5. Execute a WFI instruction.
All L1 and L2 cache disabling, L1 and L2 cache flushing, and communication with the L3 memory
system is performed in hardware after the WFI is executed, under the direction of the power controller.
Note
Executing any WFI instruction when the CPUPWRCTLR.CORE_PWRDN_EN bit is set automatically
masks out all interrupts and wake-up events in the core. If executed when the
CPUPWRCTLR.CORE_PWRDN_EN bit is set the WFI never wakes up and the core needs to be reset to
restart.
For information about cluster powerdown, see the Arm
®
DynamIQ
™
Shared Unit Technical Reference
Manual.
Core powerup
To bring a core into coherence after reset, no software steps are required.
Related references
B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1 on page B2-188
A4 Power management
A4.9 Power up and down sequences
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core