ARM Cortex-A76 Core User Manual

C4.5 Programming and reading ETM trace unit registers
You program and read the ETM trace unit registers using the Debug APB interface.
The core does not have to be in debug state when you program the ETM trace unit registers.
When you are programming the ETM trace unit registers, you must enable all the changes at the same
time. Otherwise, if you program the counter, it might start to count based on incorrect events before the
correct setup is in place for the trigger condition.
To disable the ETM trace unit, use the TRCPRGCTLR.EN bit.
Start
Set main enable bit in
TRCPRGCTLR to 0b0
Read TRCSTATR
Is TRCSTATR Idle
0b1?
Program all trace
registers required
Set main enable bit in
TRCPRGCTLR to 0b1
Is TRCSTATR Idle
0b0?
End
Yes
Yes
No
No
Read TRCSTATR
Figure C4-2 Programming ETM trace unit registers
C4 Embedded Trace Macrocell
C4.5 Programming and reading ETM trace unit registers
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C4-397
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core