B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1
The ID_MMFR3_EL1 provides information about the memory model and memory management support
in AArch32.
Bit field descriptions
ID_MMFR3_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 12 11 8 7 04 328 27 24 23 20 19 16 15
PANCohWalkCMemSzSupersec MaintBcst BPMaint CMaintSW CMaintVA
Figure B2-59 ID_MMFR3_EL1 bit assignments
Supersec, [31:28]
Supersections. Indicates support for supersections:
0x0 Supersections supported.
CMemSz, [27:24]
Cached memory size. Indicates the size of physical memory supported by the core caches:
0x2 1TByte or more, corresponding to a 40-bit or larger physical address range.
CohWalk, [23:20]
Coherent walk. Indicates whether translation table updates require a clean to the point of
unification:
0x1 Updates to the translation tables do not require a clean to the point of unification to
ensure visibility by subsequent translation table walks.
PAN, [19:16]
Privileged Access Never.
0x2
PAN supported and new ATS1CPRP and ATS1CPWP instructions supported.
MaintBcst, [15:12]
Maintenance broadcast. Indicates whether cache, TLB, and branch predictor operations are
broadcast:
0x2 Cache, TLB, and branch predictor operations affect structures according to
shareability and defined behavior of instructions.
BPMaint, [11:8]
Branch predictor maintenance. Indicates the supported branch predictor maintenance operations.
0x2 Supported branch predictor maintenance operations are:
• Invalidate all branch predictors.
• Invalidate branch predictors by MVA.
CMaintSW, [7:4]
B2 AArch64 system registers
B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-252
Non-Confidential
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