ARM Cortex-A76 Core

D9.50 TRCOSLAR, OS Lock Access Register
The TRCOSLAR sets and clears the OS Lock, to lock out external debugger accesses to the ETM trace
unit registers.
Bit field descriptions
The TRCOSLAR is a 32-bit register.
31 1 0
OSLK
RES0
Figure D9-48 TRCOSLAR bit assignments
RES0, [31:1]
RES0 Reserved.
OSLK, [0]
OS Lock key value:
0 Unlock the OS Lock.
1 Lock the OS Lock.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCOSLAR can be accessed through the external debug interface, offset 0x300.
D9 ETM registers
D9.50 TRCOSLAR, OS Lock Access Register
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D9-560
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