ARM Cortex-A76 Core User Manual

B2.73 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1
The ID_MMFR1_EL1 provides information about the memory model and memory management support
in AArch32.
Bit field descriptions
ID_MMFR1_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
BPred L1TstCln L1Uni L1Hvd L1UniSW L1HvdSW L1UniVA L1HvdVA
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3
0
Figure B2-57 ID_MMFR1_EL1 bit assignments
BPred, [31:28]
Indicates branch predictor management requirements:
0x4 For execution correctness, branch predictor requires no flushing at any time.
L1TstCln, [27:24]
Indicates the supported L1 Data cache test and clean operations, for Harvard or unified cache
implementation:
0x0 None supported.
L1Uni, [23:20]
Indicates the supported entire L1 cache maintenance operations, for a unified cache
implementation:
0x0 None supported.
L1Hvd, [19:16]
Indicates the supported entire L1 cache maintenance operations, for a Harvard cache
implementation:
0x0 None supported.
L1UniSW, [15:12]
Indicates the supported L1 cache line maintenance operations by set/way, for a unified cache
implementation:
0x0 None supported.
L1HvdSW, [11:8]
Indicates the supported L1 cache line maintenance operations by set/way, for a Harvard cache
implementation:
0x0 None supported.
L1UniVA, [7:4]
Indicates the supported L1 cache line maintenance operations by MVA, for a unified cache
implementation:
0x0 None supported.
L1HvdVA, [3:0]
B2 AArch64 system registers
B2.73 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-248
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core