ARM Cortex-A76 Core User Manual

Chapter D5
AArch64 PMU registers
This chapter describes the AArch64 PMU registers and shows examples of how to use them.
It contains the following sections:
• D5.1 AArch64 PMU register summary on page D5-446.
• D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0
on page D5-448.
• D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0
on page D5-451.
• D5.4 PMCR_EL0, Performance Monitors Control Register, EL0 on page D5-453.
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D5-445
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core