ARM Cortex-A76 Core

Chapter D5
AArch64 PMU registers
This chapter describes the AArch64 PMU registers and shows examples of how to use them.
It contains the following sections:
• D5.1 AArch64 PMU register summary on page D5-446.
• D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0
on page D5-448.
• D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0
on page D5-451.
• D5.4 PMCR_EL0, Performance Monitors Control Register, EL0 on page D5-453.
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D5-445
Non-Confidential