ARM Cortex-A76 Core User Manual

D5.1 AArch64 PMU register summary
The PMU counters and their associated control registers are accessible in the AArch64 Execution state
with MRS and MSR instructions.
The following table gives a summary of the Cortex-A76 PMU registers in the AArch64 Execution state.
For those registers not described in this chapter, see the Arm
®
Architecture Reference Manual Armv8, for
Armv8-A architecture profile.
Table D5-1 PMU register summary in the AArch64 Execution state
Name Type Width Reset Description
PMCR_EL0 RW 32
0x410B30XX
D5.4 PMCR_EL0,
Performance Monitors
Control Register, EL0
on page D5-453
PMCNTENSET_EL0 RW 32 UNK
Performance Monitors
Count Enable Set
Register
PMCNTENCLR_EL0 RW 32 UNK
Performance Monitors
Count Enable Clear
Register
PMOVSCLR_EL0 RW 32 UNK
Performance Monitors
Overflow Flag Status
Register
PMSWINC_EL0 WO 32 UNK
Performance Monitors
Software Increment
Register
PMSELR_EL0 RW 32 UNK
Performance Monitors
Event Counter Selection
Register
PMCEID0_EL0 RO 64
0xF7FF0F3F
D5.2 PMCEID0_EL0,
Performance Monitors
Common Event
Identification Register 0,
EL0 on page D5-448
PMCEID1_EL0 RO 64
0x0000BE7F
D5.3 PMCEID1_EL0,
Performance Monitors
Common Event
Identification Register 1,
EL0 on page D5-451
PMCCNTR_EL0 RW 64 UNK
Performance Monitors
Cycle Count Register
PMXEVTYPER_EL0 RW 32 UNK Performance Monitors
Selected Event Type and
Filter Register
D5 AArch64 PMU registers
D5.1 AArch64 PMU register summary
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D5-446
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core