ARM Cortex-A76 Core

Table D5-1 PMU register summary in the AArch64 Execution state (continued)
Name Type Width Reset Description
PMCCFILTR_EL0 RW 32 UNK
Performance Monitors
Cycle Count Filter
Register
PMXEVCNTR_EL0 RW 32 UNK Performance Monitors
Selected Event Count
Register
PMUSERENR_EL0 RW 32 UNK
Performance Monitors
User Enable Register
PMINTENSET_EL1 RW 32 UNK
Performance Monitors
Interrupt Enable Set
Register
PMINTENCLR_EL1 RW 32 UNK
Performance Monitors
Interrupt Enable Clear
Register
PMOVSSET_EL0 RW 32 UNK Performance Monitors
Overflow Flag Status Set
Register
PMEVCNTR0_EL0 RW 32 UNK Performance Monitors
Event Count Registers
PMEVCNTR1_EL0 RW 32 UNK
PMEVCNTR2_EL0 RW 32 UNK
PMEVCNTR3_EL0 RW 32 UNK
PMEVCNTR4_EL0 RW 32 UNK
PMEVCNTR5_EL0 RW 32 UNK
PMEVTYPER0_EL0 RW 32 UNK
Performance Monitors
Event Type Registers
PMEVTYPER1_EL0 RW 32 UNK
PMEVTYPER2_EL0 RW 32 UNK
PMEVTYPER3_EL0 RW 32 UNK
PMEVTYPER4_EL0 RW 32 UNK
PMEVTYPER5_EL0 RW 32 UNK
PMCCFILTR_EL0 RW 32 UNK
Performance Monitors
Cycle Count Filter
Register
Related references
C2.3 PMU events on page C2-374
D5 AArch64 PMU registers
D5.1 AArch64 PMU register summary
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