ARM Cortex-A76 Core User Manual

C4.7 Interaction with the PMU and Debug
This section describes the interaction with the PMU and the effect of debug double lock on trace register
access.
Interaction with the PMU
The Cortex-A76 core includes a PMU that enables events, such as cache misses and instructions
executed, to be counted over a period of time.
The PMU and ETM trace unit function together.
Use of PMU events by the ETM trace unit
The PMU architectural events described in C2.3 PMU events on page C2-374 are available to the ETM
trace unit through the extended input facility.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information about PMU events.
The ETM trace unit uses four extended external input selectors to access the PMU events. Each selector
can independently select one of the PMU events, that are then active for the cycles where the relevant
events occur. These selected events can then be accessed by any of the event registers within the ETM
trace unit. The PMU event table describes the PMU events.
Related references
C2.3 PMU events on page C2-374
C4 Embedded Trace Macrocell
C4.7 Interaction with the PMU and Debug
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core