ARM Cortex-A76 Core

B2.88 RMR_EL3, Reset Management Register
The RMR_EL3 controls the execution state that the core boots into and allows request of a Warm reset.
Bit field descriptions
RMR_EL3 is a 32-bit register, and is part of the Reset management registers functional group.
31 012
RR
RES0
RES1
Figure B2-72 RMR_EL3 bit assignments
RES0, [31:2]
RES0 Reserved.
RR, [1]
Reset Request. The possible values are:
0 This is the reset value on both a Warm and a Cold reset.
1 Requests a Warm reset.
The bit is strictly a request.
RES1, [0]
RES1 Reserved.
Configurations
There are no configuration notes.
Details that are not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.88 RMR_EL3, Reset Management Register
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