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ARM Cortex-A76 Core User Manual

ARM Cortex-A76 Core
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C4.3 ETM trace unit functional description
This section describes the functionality of the ETM trace unit.
The following figure shows the main functional blocks of the ETM trace unit.
Trace out
FIFO
Debug APB
Filtering and triggering
resources
Trace generation
Core interface
block
Core
interface
ATB
CORECLK
ETM
Figure C4-1 ETM functional blocks
Core interface
This block monitors the behavior of the core and generates P0 elements that are essentially
executed branches and exceptions traced in program order.
Trace generation
The trace generation block generates various trace packets based on P0 elements.
Filtering and triggering resources
You can limit the amount of trace data generated by the ETM through the process of filtering.
For example, generating trace only in a certain address range. More complicated logic analyzer
style filtering options are also available.
The ETM trace unit can also generate a trigger that is a signal to the trace capture device to stop
capturing trace.
FIFO
The trace generated by the ETM trace unit is in a highly-compressed form.
The FIFO enables trace bursts to be flattened out. When the FIFO becomes full, the FIFO
signals an overflow. The trace generation logic does not generate any new trace until the FIFO is
emptied. This causes a gap in the trace when viewed in the debugger.
Trace out
Trace from FIFO is output on the AMBA ATB interface.
C4 Embedded Trace Macrocell
C4.3 ETM trace unit functional description
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
C4-395
Non-Confidential

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ARM Cortex-A76 Core Specifications

General IconGeneral
ArchitectureARMv8.2-A
MicroarchitectureCortex-A76
Pipeline Depth13 stages
FrequencyUp to 3.0 GHz
Process Technology7nm
Core TypeOut-of-order
NEONYes
Power EfficiencyImproved over Cortex-A75
Performance Improvement35% over Cortex-A75
Core Count1-4 cores per cluster
ISA SupportAArch64 and AArch32
Branch PredictionYes
L1 Data Cache32KB, per core
L2 Cache256KB or 512KB, per core
L3 CacheUp to 4MB
Memory SupportLPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)DynamIQ Shared Unit (DSU)
Cryptography ExtensionsYes
Virtualization SupportYes
L1 Cache64 KB per core

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