ARM Cortex-A76 Core User Manual

D9.26 TRCEVENTCTL0R, Event Control 0 Register
The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the
external outputs from the ETM trace unit. The events are selected from the Resource Selectors.
Bit field descriptions
The TRCEVENTCTL0R is a 32-bit register.
31 16 15 14 12 11 8 7 4 3 0
TYPE3
SEL1
30 28 27 24 23 22 20 19
SEL3 SEL2
TYPE2 TYPE0TYPE1
SEL0
6
RES0
Figure D9-24 TRCEVENTCTL0R bit assignments
TYPE3, [31]
Selects the resource type for trace event 3:
0 Single selected resource.
1 Boolean combined resource pair.
RES0, [30:28]
RES0 Reserved.
SEL3, [27:24]
Selects the resource number, based on the value of TYPE3:
When TYPE3 is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When TYPE3 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
TYPE2, [23]
Selects the resource type for trace event 2:
0 Single selected resource.
1 Boolean combined resource pair.
RES0, [22:20]
RES0 Reserved.
SEL2, [19:16]
Selects the resource number, based on the value of TYPE2:
When TYPE2 is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When TYPE2 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
TYPE1, [15]
Selects the resource type for trace event 1:
0 Single selected resource.
1 Boolean combined resource pair.
RES0, [14:12]
D9 ETM registers
D9.26 TRCEVENTCTL0R, Event Control 0 Register
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core