EasyManua.ls Logo

ARM Cortex-A76 Core

ARM Cortex-A76 Core
602 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
RES0 Reserved.
SEL1, [11:8]
Selects the resource number, based on the value of TYPE1:
When TYPE1 is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
TYPE0, [7]
Selects the resource type for trace event 0:
0 Single selected resource.
1 Boolean combined resource pair.
RES0, [6:4]
RES0 Reserved.
SEL0, [3:0]
Selects the resource number, based on the value of TYPE0:
When TYPE0 is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When TYPE0 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCEVENTCTL0R can be accessed through the external debug interface, offset 0x020.
D9 ETM registers
D9.26 TRCEVENTCTL0R, Event Control 0 Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-531
Non-Confidential

Table of Contents

Related product manuals