ARM Cortex-A76 Core User Manual

RES0 Reserved.
SEL1, [11:8]
Selects the resource number, based on the value of TYPE1:
When TYPE1 is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
TYPE0, [7]
Selects the resource type for trace event 0:
0 Single selected resource.
1 Boolean combined resource pair.
RES0, [6:4]
RES0 Reserved.
SEL0, [3:0]
Selects the resource number, based on the value of TYPE0:
When TYPE0 is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When TYPE0 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCEVENTCTL0R can be accessed through the external debug interface, offset 0x020.
D9 ETM registers
D9.26 TRCEVENTCTL0R, Event Control 0 Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-531
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core