ARM Cortex-A76 Core User Manual

D9.16 TRCCNTCTLR0, Counter Control Register 0
The TRCCNTCTLR0 controls the counter.
Bit field descriptions
The TRCCNTCTLR0 is a 32-bit register.
31 16 15 14 12 11 8 7 6 4 3 0
RLDSEL CNTSEL
RLDSELF CNTTYPE
17
RLDTYPE
RES0
Figure D9-15 TRCCNTCTLR0 bit assignments
RES0, [31:17]
RES0 Reserved.
RLDSELF, [16]
Defines whether the counter reloads when it reaches zero:
0 The counter does not reload when it reaches zero. The counter only reloads based on
RLDTYPE and RLDSEL.
1 The counter reloads when it reaches zero and the resource selected by CNTTYPE and
CNTSEL is also active. The counter also reloads based on RLDTYPE and RLDSEL.
RLDTYPE, [15]
Selects the resource type for the reload:
0 Single selected resource.
1 Boolean combined resource pair.
RES0, [14:12]
RES0 Reserved.
RLDSEL, [11:8]
Selects the resource number, based on the value of RLDTYPE:
When RLDTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When RLDTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
CNTTYPE, [7]
Selects the resource type for the counter:
0 Single selected resource.
1 Boolean combined resource pair.
RES0, [6:4]
RES0 Reserved.
D9 ETM registers
D9.16 TRCCNTCTLR0, Counter Control Register 0
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reserved.
D9-515
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core