ARM Cortex-A76 Core User Manual

D9.33 TRCIDR4, ID Register 4
The TRCIDR4 indicates the resources available in the ETM trace unit.
Bit field descriptions
The TRCIDR4 is a 32-bit register.
31 02324 16 15 8 7 342728 20 19
NUMDVCNUMPCNUMSSCCNUMCIDC
NUMACPAIRS
91112
NUMRSPAIRS
NUMVMIDC
SUPPDAC
RES0
Figure D9-31 TRCIDR4 bit assignments
NUMVMIDC, [31:28]
Indicates the number of VMID comparators available for tracing:
0x1 One VMID comparator is available.
NUMCIDC, [27:24]
Indicates the number of CID comparators available for tracing:
0x1 One Context ID comparator is available.
NUMSSCC, [23:20]
Indicates the number of single-shot comparator controls available for tracing:
0x1 One single-shot comparator control is available.
NUMRSPAIRS, [19:16]
Indicates the number of resource selection pairs available for tracing:
0x7 Eight resource selection pairs are available.
NUMPC, [15:12]
Indicates the number of core comparator inputs available for tracing:
0x0 Core comparator inputs are not implemented.
RES0, [11:9]
RES0 Reserved.
SUPPDAC, [8]
Indicates whether the implementation supports data address comparisons: This value is:
0 Data address comparisons are not implemented.
NUMDVC, [7:4]
Indicates the number of data value comparators available for tracing:
0x0 Data value comparators not implemented.
NUMACPAIRS, [3:0]
Indicates the number of address comparator pairs available for tracing:
D9 ETM registers
D9.33 TRCIDR4, ID Register 4
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D9-541
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core