ARM Cortex-A76 Core User Manual

0 TRCSYNCPR is read-write so software can change the synchronization period.
TRCERR, [24]
Indicates whether TRCVICTLR.TRCERR is implemented:
1 TRCVICTLR.TRCERR is implemented.
EXLEVEL_NS, [23:20]
Each bit controls whether instruction tracing in Non-secure state is implemented for the
corresponding Exception level:
0b0111 Instruction tracing is implemented for Non-secure EL0, EL1, and EL2 Exception
levels.
EXLEVEL_S, [19:16]
Each bit controls whether instruction tracing in Secure state is implemented for the
corresponding Exception level:
0b1011 Instruction tracing is implemented for Secure EL0, EL1, and EL3 Exception levels.
RES0, [15:12]
RES0 Reserved.
CCITMIN, [11:0]
The minimum value that can be programmed in TRCCCCTLR.THRESHOLD:
0x004 Instruction trace cycle counting minimum threshold is 4.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCIDR3 can be accessed through the external debug interface, offset 0x1EC.
D9 ETM registers
D9.32 TRCIDR3, ID Register 3
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-540
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core