ARM Cortex-A76 Core User Manual

D9.17 TRCCNTCTLR1, Counter Control Register 1
The TRCCNTCTLR1 controls the counter.
Bit field descriptions
The TRCCNTCTLR1 is a 32-bit register.
31 16 15 14 12 11 8 7 6 4 3 0
RLDSEL CNTSEL
RLDSELF
CNTTYPE
1718
CNTCHAIN
RLDTYPE
RES0
Figure D9-16 TRCCNTCTLR1 bit assignments
RES0, [31:18]
RES0 Reserved.
CNTCHAIN, [17]
Defines whether the counter decrements when the counter reloads. This enables two counters to
be used in combination to provide a larger counter:
0 The counter operates independently from the counter. The counter only decrements
based on CNTTYPE and CNTSEL.
1 The counter decrements when the counter reloads. The counter also decrements when
the resource selected by CNTTYPE and CNTSEL is active.
RLDSELF, [16]
Defines whether the counter reloads when it reaches zero:
0 The counter does not reload when it reaches zero. The counter only reloads based on
RLDTYPE and RLDSEL.
1 The counter reloads when it is zero and the resource selected by CNTTYPE and
CNTSEL is also active. The counter also reloads based on RLDTYPE and RLDSEL.
RLDTYPE, [15]
Selects the resource type for the reload:
0 Single selected resource.
1 Boolean combined resource pair.
RES0, [14:12]
RES0 Reserved.
RLDSEL, [11:8]
Selects the resource number, based on the value of RLDTYPE:
When RLDTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When RLDTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
CNTTYPE, [7]
Selects the resource type for the counter:
D9 ETM registers
D9.17 TRCCNTCTLR1, Counter Control Register 1
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D9-517
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core