ARM Cortex-A76 Core User Manual

B2.19 CLIDR_EL1, Cache Level ID Register, EL1
The CLIDR_EL1 identifies the type of cache, or caches, implemented at each level, up to a maximum of
seven levels.
It also identifies the Level of Coherency (LoC) and Level of Unification (LoU) for the cache hierarchy.
Bit field descriptions
CLIDR_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Ctype3 Ctype2 Ctype1
30 29 27 26 24 23 21 20 9 8 6 5 3 2 0
LoUU LoC
ICB
63 32
RES0
LoUIS
33
Figure B2-15 CLIDR_EL1 bit assignments
RES0, [63:33]
RES0 Reserved.
ICB, [32:30]
Inner cache boundary. This field indicates the boundary between the inner and the outer domain:
0b010 L2 cache is the highest inner level.
0b011 L3 cache is the highest inner level.
LoUU, [29:27]
Indicates the Level of Unification Uniprocessor for the cache hierarchy:
0b000 No levels of cache need to cleaned or invalidated when cleaning or invalidating to the
Point of Unification. This is the value if no caches are configured.
LoC, [26:24]
Indicates the Level of Coherency for the cache hierarchy:
0b010 L3 cache is not implemented.
0b011 L3 cache is implemented.
LoUIS, [23:21]
Indicates the Level of Unification Inner Shareable (LoUIS) for the cache hierarchy.
0b000 No cache level needs cleaning to Point of Unification.
RES0, [20:9]
No cache at levels L7 down to L4.
RES0 Reserved.
Ctype3, [8:6]
Indicates the type of cache if the core implements L3 cache. If present, unified instruction and
data caches at Level 3:
B2 AArch64 system registers
B2.19 CLIDR_EL1, Cache Level ID Register, EL1
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B2-161
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core