ARM Cortex-A76 Core User Manual

0b100 Both per-core L2 and cluster L3 caches are present.
0b000 All other options.
If Ctype2 has a value of 0b000, then the value of Ctype3 must be ignored.
Ctype2, [5:3]
Indicates the type of unified instruction and data caches at Level 2:
0b100 Either per-core L2 or cluster L2 cache is present.
0b000 All other options.
Ctype1, [2:0]
Indicates the type of cache implemented at L1:
0b011 Separate instruction and data caches at L1.
Configurations
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.19 CLIDR_EL1, Cache Level ID Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-162
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core