ARM Cortex-A76 Core User Manual

B4.21 ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2
ICH_HCR_EL2 controls the environment for VMs.
Bit field descriptions
ICH_HCR_EL2 is a 32-bit register and is part of:
• The GIC system registers functional group.
• The Virtualization registers functional group.
• The GIC host interface control registers functional group.
31
0
125678101113141526
En
UIE
NPIE
VGrp0EIE
VGrp0DIE
RES0
34
VGrp1EIE
VGrp1DIE
TDIR
1227
EOIcount
TSEI
TALL1
TALL0
TC
LRENPIE
Figure B4-11 ICH_HCR_EL2 bit assignments
EOIcount, [31:27]
Number of outstanding deactivates.
RES0, [26:15]
Reserved, RES0.
TDIR, [14]
Trap Non-secure EL1 writes to ICC_DIR_EL1 and ICV_DIR_EL1. The possible values are:
0x0 Non-secure EL1 writes of ICC_DIR_EL1 and ICV_DIR_EL1 are not trapped to
EL2, unless trapped by other mechanisms.
0x1 Non-secure EL1 writes of ICC_DIR_EL1 and ICV_DIR_EL1 are trapped to EL2.
TSEI, [13]
Trap all locally generated SEIs. The value is:
0 Locally generated SEIs do not cause a trap to EL2.
TALL1, [12]
Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 1 interrupts
to EL2. The possible values are:
0x0 Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts
proceed as normal.
0x1 Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts trap
to EL2.
TALL0, [11]
Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 0 interrupts
to EL2. The possible values are:
B4 GIC registers
B4.21 ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B4-338
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core