ARM Cortex-A76 Core User Manual

0x0 Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 0 interrupts
proceed as normal.
0x1 Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 0 interrupts trap
to EL2.
TC, [10]
Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1
to EL2. The possible values are:
0x0 Non-secure EL1 accesses to common registers proceed as normal.
0x1 Non-secure EL1 accesses to common registers trap to EL2.
RES0, [9:8]
Reserved, RES0.
VGrp1DIE, [7]
VM Group 1 Disabled Interrupt Enable. The possible values are:
0 Maintenance interrupt disabled.
1 Maintenance interrupt signaled when ICH_VMCR_EL2.VENG1 is 0.
VGrp1EIE, [6]
VM Group 1 Enabled Interrupt Enable. The possible values are:
0 Maintenance interrupt disabled.
1 Maintenance interrupt signaled when ICH_VMCR_EL2.VENG1 is 1.
VGrp0DIE, [5]
VM Group 0 Disabled Interrupt Enable. The possible values are:
0 Maintenance interrupt disabled.
1 Maintenance interrupt signaled when ICH_VMCR_EL2.VENG0 is 0.
VGrp0EIE, [4]
VM Group 0 Enabled Interrupt Enable. The possible values are:
0 Maintenance interrupt disabled.
1 Maintenance interrupt signaled when ICH_VMCR_EL2.VENG0 is 1.
NPIE, [3]
No Pending Interrupt Enable. The possible values are:
0 Maintenance interrupt disabled.
1 Maintenance interrupt signaled while the List registers contain no interrupts in the
pending state.
LRENPIE, [2]
List Register Entry Not Present Interrupt Enable. The possible values are:
0 Maintenance interrupt disabled.
1 Maintenance interrupt is asserted while the EOIcount field is not 0.
B4 GIC registers
B4.21 ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2
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B4-339
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core