ARM Cortex-A76 Core

To Next Page

To Previous Page

UIE, [1]

Underflow Interrupt Enable. The possible values are:

0 Maintenance interrupt disabled.

1 Maintenance interrupt is asserted if none, or only one, of the List register entries is

marked as a valid interrupt.

En, [0]

Enable. The possible values are:

0 Virtual CPU interface operation disabled.

1 Virtual CPU interface operation enabled.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm

Generic Interrupt Controller Architecture Specification.

B4 GIC registers

B4.21 ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2

reserved.

B4-340

Non-Confidential

Main Page

Default Chapter5
- Table of Contents5
Preface15
- About this Book16
- Feedback21
Part a Functional Description23
Chapter A125
Introduction25
- A1.1 about the Core26
- A1.2 Features27
- A1.3 Implementation Options28
- Supported Standards and Specifications29
- A1.5 Test Features30
- A1.6 Design Tasks31
- A1.7 Product Revisions32
Chapter A233
Technical Overview33
- A2.1 Components34
- A2.2 Interfaces38
- A2.3 about System Control39
- A2.4 about the Generic Timer40
Chapter A341
Clocks, Resets, and Input Synchronization41
- A3.1 about Clocks, Resets, and Input Synchronization41
- About Clocks, Resets, and Input Synchronization42
- A3.2 Asynchronous Interface43
Chapter A445
Power Management45
- A4.1 about Power Management46
- A4.2 Voltage Domains47
- A4.3 Power Domains48
- A4.4 Architectural Clock Gating Modes50
- A4.5 Power Control52
- A4.6 Core Power Modes53
- A4.7 Encoding for Power Modes56
- A4.8 Power Domain States for Power Modes57
- A4.9 Power up and down Sequences58
- A4.10 Debug over Powerdown59
Chapter A561
Memory Management Unit61
- A5.1 about the MMU62
- A5.2 TLB Organization64
- A5.3 TLB Match Process65
- A5.4 Translation Table Walks66
- A5.5 MMU Memory Accesses67
- A5.6 Specific Behaviors on Aborts and Memory Attributes68
Chapter A671
Level 1 Memory System71
- A6.1 about the L1 Memory System72
- A6.2 Cache Behavior73
- A6.3 L1 Instruction Memory System75
- A6.4 L1 Data Memory System77
- A6.5 Data Prefetching79
- A6.6 Direct Access to Internal Memory80
Chapter A797
Level 2 Memory System97
- A7.1 about the L2 Memory System98
- A7.2 about the L2 Cache99
- A7.3 Support for Memory Types100
Reliability, Availability, and Serviceability (RAS)101
- A8.1 Cache ECC and Parity102
- Cache Protection Behavior103
- A8.3 Uncorrected Errors and Data Poisoning105
- A8.4 RAS Error Types106
- A8.5 Error Synchronization Barrier107
- A8.6 Error Recording108
- A8.7 Error Injection109
Chapter A9111
Generic Interrupt Controller CPU Interface111
- A9.1 about the Generic Interrupt Controller CPU Interface112
- A9.2 Bypassing the CPU Interface113
Chapter A10115
Advanced SIMD and Floating-Point Support115
- A10.1 about the Advanced SIMD and Floating-Point Support116
- A10.2 Accessing the Feature Identification Registers117
Part B121
Chapter B1121
Aarch32 System Registers121
- B1.1 Aarch32 Architectural System Register Summary122
Chapter B2123
Aarch64 System Registers123
- B2.1 Aarch64 Registers126
- Aarch64 Architectural System Register Summary127
- B2.3 Aarch64 Implementation Defined Register Summary134
- Aarch64 Registers by Functional Group136
- B2.5 ACTLR_EL1, Auxiliary Control Register, EL1144
- B2.6 ACTLR_EL2, Auxiliary Control Register, EL2145
- B2.7 ACTLR_EL3, Auxiliary Control Register, EL3147
- B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1149
- B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2150
- B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3151
- B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1152
- B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2153
- B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3154
- B2.14 AIDR_EL1, Auxiliary ID Register, EL1155
- B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1156
- B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2157
- B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3158
- B2.18 CCSIDR_EL1, Cache Size ID Register, EL1159
- B2.19 CLIDR_EL1, Cache Level ID Register, EL1161
- B2.20 CPACR_EL1, Architectural Feature Access Control Register, EL1163
- B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2164
- B2.22 CPTR_EL3, Architectural Feature Trap Register, EL3165
- B2.23 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1166
- B2.24 CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1168
- B2.25 CPUCFR_EL1, CPU Configuration Register, EL1170
- B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1172
- B2.27 CPUPCR_EL3, CPU Private Control Register, EL3180
- B2.28 CPUPMR_EL3, CPU Private Mask Register, EL3182
- B2.29 CPUPOR_EL3, CPU Private Operation Register, EL3184
- B2.30 CPUPSELR_EL3, CPU Private Selection Register, EL3186
- B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1188
- B2.32 CSSELR_EL1, Cache Size Selection Register, EL1190
- B2.33 CTR_EL0, Cache Type Register, EL0191
- B2.34 DCZID_EL0, Data Cache Zero ID Register, EL0193
- B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1194
- B2.36 ERRIDR_EL1, Error ID Register, EL1196
- B2.37 ERRSELR_EL1, Error Record Select Register, EL1197
- B2.38 ERXADDR_EL1, Selected Error Record Address Register, EL1198
- B2.39 ERXCTLR_EL1, Selected Error Record Control Register, EL1199
- B2.40 ERXFR_EL1, Selected Error Record Feature Register, EL1200
- B2.41 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1201
- B2.42 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1202
- ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count down Register, EL1203
  - B2.45 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1206
  - B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1207
  - B2.47 ESR_EL1, Exception Syndrome Register, EL1208
  - B2.48 ESR_EL2, Exception Syndrome Register, EL2209
  - B2.49 ESR_EL3, Exception Syndrome Register, EL3210
  - B2.50 HACR_EL2, Hyp Auxiliary Configuration Register, EL2211
  - B2.51 HCR_EL2, Hypervisor Configuration Register, EL2212
  - B2.52 ID_AA64AFR0_EL1, Aarch64 Auxiliary Feature Register 0214
  - B2.53 ID_AA64AFR1_EL1, Aarch64 Auxiliary Feature Register 1215
  - B2.54 ID_AA64DFR0_EL1, Aarch64 Debug Feature Register 0, EL1216
  - B2.55 ID_AA64DFR1_EL1, Aarch64 Debug Feature Register 1, EL1218
  - B2.56 ID_AA64ISAR0_EL1, Aarch64 Instruction Set Attribute Register 0, EL1219
  - B2.57 ID_AA64ISAR1_EL1, Aarch64 Instruction Set Attribute Register 1, EL1221
  - B2.58 ID_AA64MMFR0_EL1, Aarch64 Memory Model Feature Register 0, EL1222
  - B2.59 ID_AA64MMFR1_EL1, Aarch64 Memory Model Feature Register 1, EL1224
  - B2.60 ID_AA64MMFR2_EL1, Aarch64 Memory Model Feature Register 2, EL1226
  - B2.61 ID_AA64PFR0_EL1, Aarch64 Processor Feature Register 0, EL1227
  - B2.62 ID_AA64PFR1_EL1, Aarch64 Processor Feature Register 1, EL1229
  - B2.63 ID_AFR0_EL1, Aarch32 Auxiliary Feature Register 0, EL1230
  - B2.64 ID_DFR0_EL1, Aarch32 Debug Feature Register 0, EL1231
  - B2.65 ID_ISAR0_EL1, Aarch32 Instruction Set Attribute Register 0, EL1233
  - B2.66 ID_ISAR1_EL1, Aarch32 Instruction Set Attribute Register 1, EL1235
  - B2.67 ID_ISAR2_EL1, Aarch32 Instruction Set Attribute Register 2, EL1237
  - B2.68 ID_ISAR3_EL1, Aarch32 Instruction Set Attribute Register 3, EL1239
  - B2.69 ID_ISAR4_EL1, Aarch32 Instruction Set Attribute Register 4, EL1241
  - B2.70 ID_ISAR5_EL1, Aarch32 Instruction Set Attribute Register 5, EL1243
  - B2.71 ID_ISAR6_EL1, Aarch32 Instruction Set Attribute Register 6, EL1245
  - B2.72 ID_MMFR0_EL1, Aarch32 Memory Model Feature Register 0, EL1246
  - B2.73 ID_MMFR1_EL1, Aarch32 Memory Model Feature Register 1, EL1248
  - B2.74 ID_MMFR2_EL1, Aarch32 Memory Model Feature Register 2, EL1250
  - B2.75 ID_MMFR3_EL1, Aarch32 Memory Model Feature Register 3, EL1252
  - B2.76 ID_MMFR4_EL1, Aarch32 Memory Model Feature Register 4, EL1254
  - B2.77 ID_PFR0_EL1, Aarch32 Processor Feature Register 0, EL1256
  - B2.78 ID_PFR1_EL1, Aarch32 Processor Feature Register 1, EL1258
  - B2.79 ID_PFR2_EL1, Aarch32 Processor Feature Register 2, EL1260
  - B2.80 LORC_EL1, Loregion Control Register, EL1261
  - B2.81 LORID_EL1, Loregion ID Register, EL1262
  - B2.82 LORN_EL1, Loregion Number Register, EL1263
  - B2.83 MDCR_EL3, Monitor Debug Configuration Register, EL3264
  - B2.84 MIDR_EL1, Main ID Register, EL1266
  - B2.85 MPIDR_EL1, Multiprocessor Affinity Register, EL1267
  - B2.86 PAR_EL1, Physical Address Register, EL1269
  - B2.87 REVIDR_EL1, Revision ID Register, EL1270
  - B2.88 RMR_EL3, Reset Management Register271
  - B2.89 RVBAR_EL3, Reset Vector Base Address Register, EL3272
  - B2.90 SCTLR_EL1, System Control Register, EL1273
  - B2.91 SCTLR_EL2, System Control Register, EL2275
  - B2.92 SCTLR_EL3, System Control Register, EL3276
  - B2.93 TCR_EL1, Translation Control Register, EL1278
  - B2.94 TCR_EL2, Translation Control Register, EL2279
  - B2.95 TCR_EL3, Translation Control Register, EL3280
  - B2.96 TTBR0_EL1, Translation Table Base Register 0, EL1281
  - B2.97 TTBR0_EL2, Translation Table Base Register 0, EL2282
  - B2.98 TTBR0_EL3, Translation Table Base Register 0, EL3283
  - B2.99 TTBR1_EL1, Translation Table Base Register 1, EL1284
  - B2.100 TTBR1_EL2, Translation Table Base Register 1, EL2285
  - B2.101 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2286
  - B2.102 VSESR_EL2, Virtual Serror Exception Syndrome Register287
  - B2.103 VTCR_EL2, Virtualization Translation Control Register, EL2288
  - B2.104 VTTBR_EL2, Virtualization Translation Table Base Register, EL2289
  - B3.1 Error System Register Summary292
  - B3.2 ERR0ADDR, Error Record Address Register293
  - B3.3 ERR0CTLR, Error Record Control Register294
  - B3.4 ERR0FR, Error Record Feature Register296
  - B3.5 ERR0MISC0, Error Record Miscellaneous Register 0298
  - B3.6 ERR0MISC1, Error Record Miscellaneous Register 1301
  - B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count down Register302
  - B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register303
  - B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register305
  - B3.10 ERR0STATUS, Error Record Primary Status Register307
  - B4.1 CPU Interface Registers313
  - B4.2 Aarch64 Physical GIC CPU Interface System Register Summary314
  - B4.5 ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0, EL1317
  - B4.6 ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1, EL1318
  - B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1319
  - B4.8 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3321
  - B4.9 ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1323
  - B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable Register, EL2324
  - B4.11 ICC_SRE_EL3, Interrupt Controller System Register Enable Register, EL3326
  - B4.12 Aarch64 Virtual GIC CPU Interface Register Summary328
  - B4.15 ICV_BPR0_EL1, Interrupt Controller Virtual Binary Point Register 0, EL1331
  - B4.16 ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1, EL1332
  - B4.17 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1333
  - B4.18 Aarch64 Virtual Interface Control System Register Summary335
  - B4.21 ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2338
  - B4.22 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register, EL2341
  - B4.23 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2343
  - B5.1 Aarch64 Register Summary346
  - B5.2 FPCR, Floating-Point Control Register347
  - B5.3 FPSR, Floating-Point Status Register349
  - B5.4 MVFR0_EL1, Media and VFP Feature Register 0, EL1351
  - B5.5 MVFR1_EL1, Media and VFP Feature Register 1, EL1353
  - B5.6 MVFR2_EL1, Media and VFP Feature Register 2, EL1355
  - B5.7 Aarch32 Register Summary357
  - B5.8 FPSCR, Floating-Point Status and Control Register358
  - C1.1 about Debug Methods365
  - C1.2 Debug Register Interfaces367
  - C1.3 Debug Events369
  - C2.1 about the PMU372
  - C2.2 PMU Functional Description373
  - C2.3 PMU Events374
  - C2.4 PMU Interrupts383
  - C2.5 Exporting PMU Events384
  - C3.1 about the AMU386
  - C3.2 Accessing the Activity Monitors387
  - C3.3 AMU Counters388
  - C3.4 AMU Events389
  - C4.1 about the ETM392
  - C4.2 ETM Trace Unit Generation Options and Resources393
  - C4.3 ETM Trace Unit Functional Description395
  - C4.4 Resetting the ETM396
  - C4.5 Programming and Reading ETM Trace Unit Registers397
  - C4.6 ETM Trace Unit Register Interfaces398
  - C4.7 Interaction with the PMU and Debug399
  - D1.1 Aarch32 Debug Register Summary403
  - D2.1 Aarch64 Debug Register Summary405
  - D2.2 Dbgbcrn_El1, Debug Breakpoint Control Registers, EL1407
  - D3.1 Memory-Mapped Debug Register Summary416
  - D3.2 EDCIDR0, External Debug Component Identification Register 0420
  - D3.3 EDCIDR1, External Debug Component Identification Register 1421
  - D3.4 EDCIDR2, External Debug Component Identification Register 2422
  - D3.5 EDCIDR3, External Debug Component Identification Register 3423
  - D3.6 EDDEVID, External Debug Device ID Register 0424
  - D3.7 EDDEVID1, External Debug Device ID Register 1425
  - D3.8 EDPIDR0, External Debug Peripheral Identification Register 0426
  - D3.9 EDPIDR1, External Debug Peripheral Identification Register 1427
  - D3.10 EDPIDR2, External Debug Peripheral Identification Register 2428
  - D3.11 EDPIDR3, External Debug Peripheral Identification Register 3429
  - D3.12 EDPIDR4, External Debug Peripheral Identification Register 4430
  - D3.13 Edpidrn, External Debug Peripheral Identification Registers 5-7431
  - D3.14 EDRCR, External Debug Reserve Control Register432
  - D4.1 Aarch32 PMU Register Summary434
  - D4.2 PMCEID0, Performance Monitors Common Event Identification Register 0436
  - D4.3 PMCEID1, Performance Monitors Common Event Identification Register 1439
  - D4.4 PMCR, Performance Monitors Control Register441
  - D5.1 Aarch64 PMU Register Summary445
  - D6.1 Memory-Mapped PMU Register Summary456
  - D6.2 PMCFGR, Performance Monitors Configuration Register460
  - D6.3 PMCIDR0, Performance Monitors Component Identification Register 0461
  - D6.4 PMCIDR1, Performance Monitors Component Identification Register 1462
  - D6.5 PMCIDR2, Performance Monitors Component Identification Register 2463
  - D6.6 PMCIDR3, Performance Monitors Component Identification Register 3464
  - D6.7 PMPIDR0, Performance Monitors Peripheral Identification Register 0465
  - D6.8 PMPIDR1, Performance Monitors Peripheral Identification Register 1466
  - D6.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2467
  - D6.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3468
  - D6.11 PMPIDR4, Performance Monitors Peripheral Identification Register 4469
  - D6.12 Pmpidrn, Performance Monitors Peripheral Identification Register 5-7470
  - D7.1 PMU Snapshot Register Summary472
  - D7.2 PMPCSSR, Snapshot Program Counter Sample Register473
  - D7.3 PMCIDSSR, Snapshot CONTEXTIDR_EL1 Sample Register474
  - D7.4 PMCID2SSR, Snapshot CONTEXTIDR_EL2 Sample Register475
  - D7.5 PMSSSR, PMU Snapshot Status Register476
  - D7.6 PMOVSSR, PMU Overflow Status Snapshot Register477
  - D7.7 PMCCNTSR, PMU Cycle Counter Snapshot Register478
  - D7.8 Pmevcntsrn, PMU Cycle Counter Snapshot Registers 0-5479
  - D7.9 PMSSCR, PMU Snapshot Capture Register480
  - D8.1 Aarch64 AMU Register Summary482
  - D8.2 AMCNTENCLR0_EL0, Activity Monitors Count Enable Clear Register, EL0483
  - D8.3 AMCNTENSET_EL0, Activity Monitors Count Enable Set Register, EL0484
  - D8.4 AMCFGR_EL0, Activity Monitors Configuration Register, EL0485
  - D8.5 AMUSERENR_EL0, Activity Monitor EL0 Enable Access, EL0487
  - D8.6 Amevcntrn_El0, Activity Monitor Event Counter Register, EL0489
  - D8.7 Amevtypern_El0, Activity Monitor Event Type Register, EL0490
  - D9.1 ETM Register Summary495
  - D9.2 Trcacatrn, Address Comparator Access Type Registers 0-7499
  - D9.3 Trcacvrn, Address Comparator Value Registers 0-7501
  - D9.4 TRCAUTHSTATUS, Authentication Status Register502
  - D9.5 TRCAUXCTLR, Auxiliary Control Register503
  - D9.6 TRCBBCTLR, Branch Broadcast Control Register505
  - D9.7 TRCCCCTLR, Cycle Count Control Register506
  - D9.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0507
  - D9.9 TRCCIDCVR0, Context ID Comparator Value Register 0508
  - D9.10 TRCCIDR0, ETM Component Identification Register 0509
  - D9.11 TRCCIDR1, ETM Component Identification Register 1510
  - D9.12 TRCCIDR2, ETM Component Identification Register 2511
  - D9.13 TRCCIDR3, ETM Component Identification Register 3512
  - D9.14 TRCCLAIMCLR, Claim Tag Clear Register513
  - D9.15 TRCCLAIMSET, Claim Tag Set Register514
  - D9.16 TRCCNTCTLR0, Counter Control Register 0515
  - D9.17 TRCCNTCTLR1, Counter Control Register 1517
  - D9.18 Trccntrldvrn, Counter Reload Value Registers 0-1519
  - D9.19 Trccntvrn, Counter Value Registers 0-1520
  - D9.20 TRCCONFIGR, Trace Configuration Register521
  - D9.21 TRCDEVAFF0, Device Affinity Register 0524
  - D9.22 TRCDEVAFF1, Device Affinity Register 1526
  - D9.23 TRCDEVARCH, Device Architecture Register527
  - D9.24 TRCDEVID, Device ID Register528
  - D9.25 TRCDEVTYPE, Device Type Register529
  - D9.26 TRCEVENTCTL0R, Event Control 0 Register530
  - D9.27 TRCEVENTCTL1R, Event Control 1 Register532
  - D9.28 TRCEXTINSELR, External Input Select Register533
  - D9.29 TRCIDR0, ID Register 0534
  - D9.30 TRCIDR1, ID Register 1536
  - D9.31 TRCIDR2, ID Register 2537
  - D9.32 TRCIDR3, ID Register 3539
  - D9.33 TRCIDR4, ID Register 4541
  - D9.34 TRCIDR5, ID Register 5543
  - D9.35 TRCIDR8, ID Register 8545
  - D9.36 TRCIDR9, ID Register 9546
  - D9.37 TRCIDR10, ID Register 10547
  - D9.38 TRCIDR11, ID Register 11548
  - D9.39 TRCIDR12, ID Register 12549
  - D9.40 TRCIDR13, ID Register 13550
  - D9.41 TRCIMSPEC0, Implementation Specific Register 0551
  - D9.42 TRCITATBIDR, Integration ATB Identification Register552
  - D9.43 TRCITCTRL, Integration Mode Control Register553
  - D9.44 TRCITIATBINR, Integration Instruction ATB in Register554
  - D9.45 TRCITIATBOUTR, Integration Instruction ATB out Register555
  - D9.46 TRCITIDATAR, Integration Instruction ATB Data Register556
  - D9.47 TRCLAR, Software Lock Access Register557
  - D9.48 TRCLSR, Software Lock Status Register558
  - D9.49 Trccntvrn, Counter Value Registers 0-1559
  - D9.50 TRCOSLAR, os Lock Access Register560
  - D9.51 TRCOSLSR, os Lock Status Register561
  - D9.52 TRCPDCR, Power down Control Register562
  - D9.53 TRCPDSR, Power down Status Register563
  - D9.54 TRCPIDR0, ETM Peripheral Identification Register 0564
  - D9.55 TRCPIDR1, ETM Peripheral Identification Register 1565
  - D9.56 TRCPIDR2, ETM Peripheral Identification Register 2566
  - D9.57 TRCPIDR3, ETM Peripheral Identification Register 3567
  - D9.58 TRCPIDR4, ETM Peripheral Identification Register 4568
  - D9.59 Trcpidrn, ETM Peripheral Identification Registers 5-7569
  - D9.60 TRCPRGCTLR, Programming Control Register570
  - D9.61 Trcrsctlrn, Resource Selection Control Registers 2-16571
  - D9.62 Trcseqevrn, Sequencer State Transition Control Registers 0-2572
  - D9.63 TRCSEQRSTEVR, Sequencer Reset Control Register574
  - D9.64 TRCSEQSTR, Sequencer State Register575
  - D9.65 TRCSSCCR0, Single-Shot Comparator Control Register 0576
  - D9.66 TRCSSCSR0, Single-Shot Comparator Status Register 0577
  - D9.67 TRCSTALLCTLR, Stall Control Register578
  - D9.68 TRCSTATR, Status Register579
  - D9.69 TRCSYNCPR, Synchronization Period Register580
  - D9.70 TRCTRACEIDR, Trace ID Register581
  - D9.71 TRCTSCTLR, Global Timestamp Control Register582
  - D9.72 TRCVICTLR, Viewinst Main Control Register583
  - D9.73 TRCVIIECTLR, Viewinst Include-Exclude Control Register585
  - D9.74 TRCVISSCTLR, Viewinst Start-Stop Control Register586
  - D9.75 TRCVMIDCVR0, VMID Comparator Value Register 0587
  - D9.76 TRCVMIDCCTLR0, Virtual Context Identifier Comparator Control Register 0588

ARM Cortex-A76 Core

Table of Contents

Related product manuals