A10.1 About the Advanced SIMD and floating-point support
The Cortex-A76 core supports the Advanced SIMD and scalar floating-point instructions in the A64
instruction set and the Advanced SIMD and floating-point instructions in the A32 and T32 instruction
sets.
The Cortex-A76 floating-point implementation:
• Does not generate floating-point exceptions.
• Implements all scalar operations in hardware with support for all combinations of:
— Rounding modes.
— Flush-to-zero.
— Default Not a Number (NaN) modes.
The Armv8-A architecture does not define a separate version number for its Advanced SIMD and
floating-point support in the AArch64 execution state because the instructions are always implicitly
present.
A10 Advanced SIMD and floating-point support
A10.1 About the Advanced SIMD and floating-point support
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A10-116
Non-Confidential
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