ARM Cortex-A76 Core User Manual

A10.1 About the Advanced SIMD and floating-point support
The Cortex-A76 core supports the Advanced SIMD and scalar floating-point instructions in the A64
instruction set and the Advanced SIMD and floating-point instructions in the A32 and T32 instruction
sets.
The Cortex-A76 floating-point implementation:
• Does not generate floating-point exceptions.
• Implements all scalar operations in hardware with support for all combinations of:
— Rounding modes.
— Flush-to-zero.
— Default Not a Number (NaN) modes.
The Armv8-A architecture does not define a separate version number for its Advanced SIMD and
floating-point support in the AArch64 execution state because the instructions are always implicitly
present.
A10 Advanced SIMD and floating-point support
A10.1 About the Advanced SIMD and floating-point support
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A10-116
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core