ARM Cortex-A76 Core User Manual

A1.3 Implementation options
All Cortex-A76 cores in the cluster must have the same build-time configuration options, except for the
L2 cache size.
The following table lists the implementation options for a core.
Table A1-1 Core implementation options
Feature Range of options Notes
L2 cache size • 128KB
• 256KB
• 512KB
-
L2 transaction queue size • 24 entries
• 36 entries
• 48 entries
There are two identical L2 banks in the
Cortex-A76 core that can be configured
with 12, 18, or 24 L2 transaction queue
entries per L2 bank.
L1 and L2 ECC or parity protection Can be included or not included. L1 and L2 error protection can only be
enabled if L3 cache error protection is
enabled.
Cryptographic Extension Can be included or not included. -
Core bus width 128-bit, 256-bit This specifies the bus width between the
core and the DSU CPU bridge. The legal
core bus width and master bus width
combinations are:
• If the core bus width is 128 bits, the
master bus interface can be any of the
following options.
— Single 128-bit wide ACE interface.
— Dual 128-bit wide ACE interfaces.
— Single 128-bit wide CHI interface.
— Single 256-bit wide CHI interface.
• If the core bus width is 256 bits, the
master bus interface is a single 256-bit
wide CHI interface.
CoreSight Embedded Logic Analyzer (ELA) Optional support Support for integrating CoreSight
ELA-500. CoreSight is a separately
licensable product.
ELA RAM Address size See the Arm
®
CoreSight
™
ELA-500
Embedded Logic Analyzer Technical
Reference Manual for the full supported
range.
The default and recommended value for
Cortex-A76 is 6.
A1 Introduction
A1.3 Implementation options
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A1-28
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core