D8.6 AMEVCNTRn_EL0, Activity Monitor Event Counter Register, EL0
The activity counters AMEVCNTRn_EL0 are directly accessible in the memory mapped-view. n is 0-4.
Bit field descriptions
The AMEVCNTRn_EL0 is a 64-bit register.
63
0
ACNT
Figure D8-3 AMEVCNTRn_EL0 bit assignments
ACNT, [63:0]
Value of the activity counter AMEVCNTRn_EL0.
This bit field resets to zero and the counters monitoring cycle events do not increment when the
core is in WFI or WFE.
Configurations
Counters might have fixed event allocation.
Usage constraints
Accessing the AMEVCNTRn_EL0
To access the AMEVCNTRn_EL0:
MRS <Xt>, AMEVCNTRn_EL0 ; Read AMEVCNTRn_EL0 into Xt
MSR AMEVCNTRn_EL0, <Xt> ; Write Xt to AMEVCNTRn_EL0
Register access is encoded as follows:
Table D8-6 AMEVCNTRn_EL0 encoding
op0 op1 CRn CRm op2
11 011 1111 1001 <0-4>
The AMEVCNTRn_EL0[63:32] can also be accessed through the external memory-mapped
interface, offset 0x004+8n. In this case, it is read-only.
The AMEVCNTRn_EL0[31:0] can also be accessed through the external memory-mapped
interface, offset 0x000+8n. In this case, it is read-only.
This register is accessible as follows:
EL0 EL1 EL2 EL3
RO RO RO RW
Traps and enables
If ACTLR_EL2.AMEN is 0, then Non-secure accesses to this register from EL0 and EL1 are
trapped to EL2.
If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped
to EL3.
If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1.
D8 AArch64 AMU registers
D8.6 AMEVCNTRn_EL0, Activity Monitor Event Counter Register, EL0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D8-489
Non-Confidential
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