B2.48 ESR_EL2, Exception Syndrome Register, EL2
The ESR_EL2 holds syndrome information for an exception taken to EL2.
Bit field descriptions
ESR_EL2 is a 32-bit register, and is part of:
• The Virtualization registers functional group.
• The Exception and fault handling registers functional group.
EC
31 0
ISS
2426 25
IL
Figure B2-35 ESR_EL2 bit assignments
EC, [31:26]
Exception Class. Indicates the reason for the exception that this register holds information
about. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for
more information.
IL, [25]
Instruction Length for synchronous exceptions. The possible values are:
0 16-bit.
1 32-bit.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information.
ISS, [24:0]
Syndrome information. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A
architecture profile for more information.
When reporting a virtual SEI, bits[24:0] take the value of VSESRL_EL2[24:0].
When reporting a physical SEI, the following occurs:
• IDS==0 (architectural syndrome).
• AET always reports an uncontainable error (UC) with value 0b000 or an unrecoverable error (UEU)
with value 0b001.
• EA is RES0.
When reporting a synchronous Data Abort, EA is RES0.
See B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register on page B2-287.
Configurations
RW fields in this register reset to architecturally UNKNOWN values.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.48 ESR_EL2, Exception Syndrome Register, EL2
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-209
Non-Confidential
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