ARM Cortex-A76 Core User Manual

D8.4 AMCFGR_EL0, Activity Monitors Configuration Register, EL0
The AMCFGR_EL0 provides information on the number of activity counters implemented and their size.
Bit field descriptions
The AMCFGR_EL0 is a 32-bit register.
31 0
N
14
8 7
RES0
SIZE
13
Figure D8-1 AMCFGR_EL0 bit assignments
RES0, [31:14]
Reserved, RES0.
SIZE, [13:8]
Size of counters, minus one.
This field defines the size of the largest counter implemented by the activity monitors. In the
Armv8-A architecture, the largest counter has 64 bits, therefore the value of this field is
0b111111.
N, [7:0]
Number of activity counters implemented, where the number of counters is N+1. The
Cortex-A76 core implements five counters, therefore the value is 0x04.
Configurations
There are no configuration notes.
Usage constraints
Accessing the AMCFGR_EL0
To access the AMCFGR_EL0:
MRS <Xt>, AMCFGR_EL0 ; Read AMCFGR_EL0 into Xt
Register access is encoded as follows:
Table D8-4 AMCFGR_EL0 encoding
op0 op1 CRn CRm op2
11 011 1111 1010 110
The AMCFGR_EL0 can be accessed through the external debug interface, offset 0xE00. In this
case, it is read-only.
This register is accessible as follows:
EL0 EL1 EL2 EL3
RO RO RO RO
D8 AArch64 AMU registers
D8.4 AMCFGR_EL0, Activity Monitors Configuration Register, EL0
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D8-485
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core