B4.20 ICH_AP1R0_EL2, Interrupt Controller Hyp Active Priorities Group 1 Register
0, EL2
The ICH_AP1R0_EL2 provides information about Group 1 active priorities for EL2.
Bit field descriptions
This register is a 32-bit register and is part of:
• The GIC system registers functional group.
• The Virtualization registers functional group.
• The GIC host interface control registers functional group.
The core implements 5 bits of priority with 32 priority levels, corresponding to the 32 bits [31:0] of the
register. The possible values for each bit are:
0x00000000 No interrupt active. This is the reset value.
0x00000001 Interrupt active for priority 0x0.
0x00000002 Interrupt active for priority 0x8.
...
0x80000000 Interrupt active for priority 0xF8.
Details that are not provided in this description are architecturally defined. See the Arm
®
Generic
Interrupt Controller Architecture Specification.
B4 GIC registers
B4.20 ICH_AP1R0_EL2, Interrupt Controller Hyp Active Priorities Group 1 Register 0, EL2
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B4-337
Non-Confidential
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