ARM Cortex-A76 Core User Manual

D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register
1, EL0
The PMCEID1_EL0 defines which common architectural and common microarchitectural feature events
are implemented.
Bit field descriptions
31
0
16
RES0
15
ID[47:32]
Figure D5-2 PMCEID1_EL0 bit assignments
RES0, [31:16]
RES0 Reserved.
ID[47:32], [15:0]
Common architectural and microarchitectural feature events that can be counted by the PMU
event counters.
For each bit described in the following table, the event is implemented if the bit is set to 1, or
not implemented if the bit is set to 0.
Table D5-3 PMU common events
Bit Event mnemonic Description
[15] L2D_TLB Attributable Level 2 data or unified TLB access.
1
This event is implemented.
[13] L2D_TLB_REFILL Attributable Level 2 data or unified TLB refill.
1
This event is implemented.
[6] L1I_TLB Level 1 instruction TLB access.
1
This event is implemented.
[5] L1D_TLB Level 1 data TLB access.
1
This event is implemented.
[4] STALL_BACKEND No operation issued due to backend.
1
This event is implemented.
[3] STALL_FRONTEND No operation issued due to frontend.
1
This event is implemented.
[2] BR_MIS_PRED_RETIRED Instruction architecturally executed, mispredicted branch.
1
This event is not implemented.
D5 AArch64 PMU registers
D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D5-451
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core