Table D5-2 PMU common events (continued)
Bit Event mnemonic Description
[9] EXC_TAKEN
Exception taken:
1
This event is implemented.
[8] INST_RETIRED
Instruction architecturally executed:
1
This event is implemented.
[7] ST_RETIRED
Instruction architecturally executed, condition check pass - store:
0
This event is not implemented.
[6] LD_RETIRED
Instruction architecturally executed, condition check pass - load:
0
This event is not implemented.
[5] L1D_TLB_REFILL
L1 Data TLB refill:
1
This event is implemented.
[4] L1D_CACHE
L1 Data cache access:
1
This event is implemented.
[3] L1D_CACHE_REFILL
L1 Data cache refill:
1
This event is implemented.
[2] L1I_TLB_REFILL
L1 Instruction TLB refill:
1
This event is implemented.
[1] L1I_CACHE_REFILL
L1 Instruction cache refill:
1
This event is implemented.
[0] SW_INCR
Instruction architecturally executed, condition check pass - software increment:
1
This event is implemented.
Note
The PMU events implemented in the above table can be found in Event number PMU event bus (to
trace) Event mnemonic Event description 0x0 [00] SW_INCR Software increment. Instruction
architecturally executed (condition code check pass). 0x1 [01] L1I_CACHE_REFILL L1 instruction
cache refill. This event counts any instruction fetch which misses in the cache. The … on page C2-374.
D5 AArch64 PMU registers
D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D5-450
Non-Confidential
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