ARM Cortex-A76 Core User Manual

Table D5-2 PMU common events (continued)
Bit Event mnemonic Description
[23] L2D_CACHE_REFILL
L2 Data cache refill:
1
This event is implemented.
[22] L2D_CACHE
L2 Data cache access:
1
This event is implemented.
[21] L1D_CACHE_WB
L1 Data cache Write-Back:
1
This event is implemented.
[20] L1I_CACHE
L1 Instruction cache access:
1
This event is implemented.
[19] MEM_ACCESS
Data memory access:
1
This event is implemented.
[18] BR_PRED
Predictable branch speculatively executed:
1
This event is implemented.
[17] CPU_CYCLES
Cycle:
1
This event is implemented.
[16] BR_MIS_PRED
Mispredicted or not predicted branch speculatively executed:
1
This event is implemented.
[15] UNALIGNED_LDST_RETIRED
Instruction architecturally executed, condition check pass - unaligned load or store:
0
This event is not implemented.
[14] BR_RETURN_RETIRED
Instruction architecturally executed, condition check pass - procedure return:
0
This event is not implemented.
[13] BR_IMMED_RETIRED
Instruction architecturally executed - immediate branch:
0
This event is not implemented.
[12] PC_WRITE_RETIRED
Instruction architecturally executed, condition check pass - software change of the PC:
0
This event is not implemented.
[11] CID_WRITE_RETIRED
Instruction architecturally executed, condition check pass - write to CONTEXTIDR:
1
This event is implemented.
[10] EXC_RETURN
Instruction architecturally executed, condition check pass - exception return:
1
This event is implemented.
D5 AArch64 PMU registers
D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D5-449
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core