ARM Cortex-A76 Core

Table D5-3 PMU common events (continued)
Bit Event mnemonic Description
[1] BR_RETIRED Instruction architecturally executed, branch.
1
This event is implemented.
[0] L2D_CACHE_ALLOCATE Level 2 data cache allocation without refill.
1
This event is implemented.
Note
The PMU events implemented in the above table can be found in Event number PMU event bus (to
trace) Event mnemonic Event description 0x0 [00] SW_INCR Software increment. Instruction
architecturally executed (condition code check pass). 0x1 [01] L1I_CACHE_REFILL L1 instruction
cache refill. This event counts any instruction fetch which misses in the cache. The … on page C2-374.
D5 AArch64 PMU registers
D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0
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