ARM Cortex-A76 Core User Manual

Table D5-3 PMU common events (continued)
Bit Event mnemonic Description
[1] BR_RETIRED Instruction architecturally executed, branch.
1
This event is implemented.
[0] L2D_CACHE_ALLOCATE Level 2 data cache allocation without refill.
1
This event is implemented.
Note
The PMU events implemented in the above table can be found in Event number PMU event bus (to
trace) Event mnemonic Event description 0x0 [00] SW_INCR Software increment. Instruction
architecturally executed (condition code check pass). 0x1 [01] L1I_CACHE_REFILL L1 instruction
cache refill. This event counts any instruction fetch which misses in the cache. The … on page C2-374.
D5 AArch64 PMU registers
D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D5-452
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core