ARM Cortex-A76 Core User Manual

• D9.24 TRCDEVID, Device ID Register on page D9-528.
• D9.25 TRCDEVTYPE, Device Type Register on page D9-529.
• D9.26 TRCEVENTCTL0R, Event Control 0 Register on page D9-530.
• D9.27 TRCEVENTCTL1R, Event Control 1 Register on page D9-532.
• D9.28 TRCEXTINSELR, External Input Select Register on page D9-533.
• D9.29 TRCIDR0, ID Register 0 on page D9-534.
• D9.30 TRCIDR1, ID Register 1 on page D9-536.
• D9.31 TRCIDR2, ID Register 2 on page D9-537.
• D9.32 TRCIDR3, ID Register 3 on page D9-539.
• D9.33 TRCIDR4, ID Register 4 on page D9-541.
• D9.34 TRCIDR5, ID Register 5 on page D9-543.
• D9.35 TRCIDR8, ID Register 8 on page D9-545.
• D9.36 TRCIDR9, ID Register 9 on page D9-546.
• D9.37 TRCIDR10, ID Register 10 on page D9-547.
• D9.38 TRCIDR11, ID Register 11 on page D9-548.
• D9.39 TRCIDR12, ID Register 12 on page D9-549.
• D9.40 TRCIDR13, ID Register 13 on page D9-550.
• D9.41 TRCIMSPEC0, Implementation Specific Register 0 on page D9-551.
• D9.42 TRCITATBIDR, Integration ATB Identification Register on page D9-552.
• D9.43 TRCITCTRL, Integration Mode Control Register on page D9-553.
• D9.44 TRCITIATBINR, Integration Instruction ATB In Register on page D9-554.
• D9.45 TRCITIATBOUTR, Integration Instruction ATB Out Register on page D9-555.
• D9.46 TRCITIDATAR, Integration Instruction ATB Data Register on page D9-556.
• D9.47 TRCLAR, Software Lock Access Register on page D9-557.
• D9.48 TRCLSR, Software Lock Status Register on page D9-558.
• D9.49 TRCCNTVRn, Counter Value Registers 0-1 on page D9-559.
• D9.50 TRCOSLAR, OS Lock Access Register on page D9-560.
• D9.51 TRCOSLSR, OS Lock Status Register on page D9-561.
• D9.52 TRCPDCR, Power Down Control Register on page D9-562.
• D9.53 TRCPDSR, Power Down Status Register on page D9-563.
• D9.54 TRCPIDR0, ETM Peripheral Identification Register 0 on page D9-564.
• D9.55 TRCPIDR1, ETM Peripheral Identification Register 1 on page D9-565.
• D9.56 TRCPIDR2, ETM Peripheral Identification Register 2 on page D9-566.
• D9.57 TRCPIDR3, ETM Peripheral Identification Register 3 on page D9-567.
• D9.58 TRCPIDR4, ETM Peripheral Identification Register 4 on page D9-568.
• D9.59 TRCPIDRn, ETM Peripheral Identification Registers 5-7 on page D9-569.
• D9.60 TRCPRGCTLR, Programming Control Register on page D9-570.
• D9.61 TRCRSCTLRn, Resource Selection Control Registers 2-16 on page D9-571.
• D9.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2 on page D9-572.
• D9.63 TRCSEQRSTEVR, Sequencer Reset Control Register on page D9-574.
• D9.64 TRCSEQSTR, Sequencer State Register on page D9-575.
• D9.65 TRCSSCCR0, Single-Shot Comparator Control Register 0 on page D9-576.
• D9.66 TRCSSCSR0, Single-Shot Comparator Status Register 0 on page D9-577.
• D9.67 TRCSTALLCTLR, Stall Control Register on page D9-578.
• D9.68 TRCSTATR, Status Register on page D9-579.
• D9.69 TRCSYNCPR, Synchronization Period Register on page D9-580.
• D9.70 TRCTRACEIDR, Trace ID Register on page D9-581.
• D9.71 TRCTSCTLR, Global Timestamp Control Register on page D9-582.
• D9.72 TRCVICTLR, ViewInst Main Control Register on page D9-583.
• D9.73 TRCVIIECTLR, ViewInst Include-Exclude Control Register on page D9-585.
• D9.74 TRCVISSCTLR, ViewInst Start-Stop Control Register on page D9-586.
• D9.75 TRCVMIDCVR0, VMID Comparator Value Register 0 on page D9-587.
• D9.76 TRCVMIDCCTLR0, Virtual context identifier Comparator Control Register 0 on page D9-588.
D9 ETM registers
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
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D9-494
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core