ARM Cortex-A76 Core User Manual

Chapter D9
ETM registers
This chapter describes the ETM registers.
It contains the following sections:
• D9.1 ETM register summary on page D9-495.
• D9.2 TRCACATRn, Address Comparator Access Type Registers 0-7 on page D9-499.
• D9.3 TRCACVRn, Address Comparator Value Registers 0-7 on page D9-501.
• D9.4 TRCAUTHSTATUS, Authentication Status Register on page D9-502.
• D9.5 TRCAUXCTLR, Auxiliary Control Register on page D9-503.
• D9.6 TRCBBCTLR, Branch Broadcast Control Register on page D9-505.
• D9.7 TRCCCCTLR, Cycle Count Control Register on page D9-506.
• D9.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0 on page D9-507.
• D9.9 TRCCIDCVR0, Context ID Comparator Value Register 0 on page D9-508.
• D9.10 TRCCIDR0, ETM Component Identification Register 0 on page D9-509.
• D9.11 TRCCIDR1, ETM Component Identification Register 1 on page D9-510.
• D9.12 TRCCIDR2, ETM Component Identification Register 2 on page D9-511.
• D9.13 TRCCIDR3, ETM Component Identification Register 3 on page D9-512.
• D9.14 TRCCLAIMCLR, Claim Tag Clear Register on page D9-513.
• D9.15 TRCCLAIMSET, Claim Tag Set Register on page D9-514.
• D9.16 TRCCNTCTLR0, Counter Control Register 0 on page D9-515.
• D9.17 TRCCNTCTLR1, Counter Control Register 1 on page D9-517.
• D9.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1 on page D9-519.
• D9.19 TRCCNTVRn, Counter Value Registers 0-1 on page D9-520.
• D9.20 TRCCONFIGR, Trace Configuration Register on page D9-521.
• D9.21 TRCDEVAFF0, Device Affinity Register 0 on page D9-524.
• D9.22 TRCDEVAFF1, Device Affinity Register 1 on page D9-526.
• D9.23 TRCDEVARCH, Device Architecture Register on page D9-527.
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core