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B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control

ERRSELR_EL1.SEL.

If ERRSELR_EL1.SEL==0, then ERXPFGCTLR_EL1 accesses the ERR0PFGCTLR register of the core

error record. See B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register

on page B3-303.

If ERRSELR_EL1.SEL==1, then ERXPFGCTLR_EL1 accesses the ERR1PFGCTLR register of the

DSU error record. See the Arm

DynamIQ

™

Shared Unit Technical Reference Manual.

Configurations

There are no configuration notes.

Accessing the ERXPFGCTLR_EL1

This register can be read using MRS with the following syntax:

MRS <syntax>

This register can be written using MSR with the following syntax:

MSR <syntax>

This syntax is encoded with the following settings in the instruction encoding:

<systemreg> op0 op1 CRn CRm op2

S3_0_C15_C2_1 11 000 1111 0010 001

Accessibility

This register is accessible in software as follows:

<syntax> Control Accessibility

E2H TGE NS EL0 EL1 EL2 EL3

S3_0_C15_C2_1 x x 0 - RW n/a RW

S3_0_C15_C2_1 x 0 1 - RW RW RW

S3_0_C15_C2_1 x 1 1 - n/a RW RW

'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.

B2 AArch64 system registers

B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1

reserved.

B2-204

Non-Confidential

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